1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a one-shot pulse signal generation circuitry for use in a semiconductor memory integrated circuit. In this specification, the one-shot pulse signal will be called an "OS signal".
2. Description of Related Art
A typical example of conventional OS signal generation circuitry for use in a semiconductor memory integrated circuit comprises "n" external address inputs A.sub.1 to An (where "n" is positive integer) for receiving an address of "n" bits, and the same number of OS signal generating circuits each having an input connected to a corresponding one of the external address inputs and generating an individual OS signal in response to a logical level transition of a corresponding address bit. An output of all the individual OS signal generating circuits is connected to inputs of an OR circuit, which generates an output OS signal.
In this conventional OS signal generation circuitry, a P/N ratio in each logic circuit receiving one corresponding address bit substantially changes dependently upon whether the address of "n" bits changes in only one bit or in a plurality of bits, namely in accordance with the number of address bits actually changing their logical level. Here, the P/N ratio can be defined to mean a ratio of a current driving capacity of a turned-on P-channel transistor to a current driving capacity of a turned-on N-channel transistor in a MOS transistor circuit.
Because of the change of the P/N ratio, a logical threshold voltage level in each logic circuit correspondingly changes. As a result, a one-shot pulse width of the output OS signal changes dependently upon the number of address bits actually changing their logical level. In a semiconductor memory circuit in which an internal operation is controlled by the output OS signal, an access time is dependent upon the timing of the rising of the OS signal and the pulse width of the OS signal. Here, the access time can be defined to mean a length of time from the moment an address is established to the moment an output data becomes effective. Therefore, the access time depends upon which of the "n" address bits actually changes and upon the number of address bits actually changing their logical level. Namely, the access time has a dependency to the address.